Modern CMOS active pixel sensor (APS) designs can benefit significantly from having embedded cache memory in close proximity to the sensor array and more preferably, on the same die. Use of such embedded cache memory is not, however, without tradeoffs. For example, the memory elements and related logic periphery circuits require the use of die area that might otherwise be used for the image sensor array. For arrays with an equivalent number of pixels, a reduction in the size of the sensor array results in a reduction of the photo-active area of each pixel which directly results in reduced photo conversion efficiency. Additionally, reduced pixel area may not be desirable for high-performance sensors that require large fill factors for low noise and low light performance. Typical static RAM (SRAM) implementations of embedded cache memory are area intensive thereby exacerbating these problems.
Because the area requirements of SRAM cache are so large, embedded cache memories in various devices typically have used dynamic RAM (DRAM) caches. Conventional DRAM memories are not well suited for embedded memory due to the requirement for a relatively large capacitor for each cell and the specialized process required for fabricating such capacitors. Embedding memory in a CMOS process has, therefore, turned to alternative methods of fabricating memory cells that do not require a capacitor. FIG. 1 depicts a prior art DRAM cell 100 fabricated on a silicon-on-insulator (SOI) CMOS process. The memory cell 100 is constructed by two MOS transistors in series and sharing the same gate. The first MOS transistor is an NMOS device formed by a write bit line 110, a buried word line 115, a floating body storage node 120 and a shared word line gate 105. This NMOS transistor is used to store a data value in the form of charge on the storage node 120. The second MOS transistor is a PMOS device formed with the buried word line 115, the storage node 120, the read bit line 135 and the shared word line gate 105. This PMOS transistor is used to read the logic value from the storage node 120. The use of such a memory cell 100 in image sensors is not, however, without problems. The memory cell 100 requires a SOI substrate, which is expensive and not ordinarily a feature of CMOS APS process technologies. Also, and as is described in U.S. Pat. No. 5,448,513 to Hu et al., the memory cell 100 requires a relatively complex control scheme that requires the cell to be purged before writing any data value irrespective of the logic level to be written. Lastly, single-gated floating body effect based devices face serious challenges for scaling below 50 nm feature sizes.
FIG. 2 illustrates a prior art DRAM cell 200 that also utilizes an SOI CMOS process. The DRAM cell 200 features a drain 215, a gate 210 and a source 205 along with a floating body storage node region 220. A memory value is stored on the floating body storage node region 220 when a high-energy carrier undergoes a collision (scattering event) with the lattice of the floating body region near the boundary with the drain 215. For example, a high energy electron in the conduction band undergoes a scattering event and liberates an electron from the valence band, which results in the initial electron lowering its energy (i.e. its energy is transferred to the valence band electron) and a new electron/hole pair is formed in the floating body region. The electrons are swept out of the floating body leaving behind excess holes. These holes may recombine or diffuse but do so relatively slowly due to the presence of the buried oxide layer 225. As a result, when the transistor 200 is turned off, the excess holes are trapped in the floating body storage node region 220 and represent the stored logic level. Although, the prior art cell 200 is an improvement over the memory cell 1 of FIG. 1 in that it is comprised of only a single transistor and thus will generally require less area, the planar nature of the device nevertheless presents similar issues with regard to scaling below 50 nm. Also, the DRAM cell 200 relies exclusively on impact ionization for generation of storage node carriers. Using only impact ionization for generating these carriers consumes a lot of power because the required drain current may be orders of magnitude greater than the hole current it supports. Also, impact ionization is strongly temperature dependent and decreases at higher temperatures due to increased lattice scattering thus leading to lower overall efficiency. Device reliability may also be compromised by hot electron effect or electron migration due to the high carrier energy required for ionization.
There is therefore a need for an embedded DRAM cell capable of scaling below 50 nm without the need for SOI processes and without being wholly dependent on impact ionization.